Samsung shifts focus to DTCO as 2nm process hits limits
Samsung Electronics said process miniaturization alone yields only 10 to 15 percent performance gains as the semiconductor industry approaches physical limits. Foundry Vice President Shin Jong-shin told attendees at a Seoul workshop on Wednesday that Design and Process Integration Optimization will account for half of all improvements at 3 nanometers and below, up from 10 percent at 7 nanometers.
The South Korean manufacturer shifted from FinFET transistors to Gate-All-Around structures at its 3nm node and plans third-generation 2nm production within two years. Engineers modify manufacturing constraints based on client requirements to reduce chip surface area and power consumption while using artificial intelligence to generate new cell designs.
Shin said even 1 to 2 percent performance differences influence foundry selection decisions, unlike artificial intelligence applications, where capabilities double within months. Samsung postponed its 1.4nm technology to refine its current 2nm processes through System-Process Co-Optimization and System-Design-Process Co-Optimization.
